Jobs: (EXPERIENCED) Walk-In @ "INFOTECH" : ASIC & FPGA : On 24, 25 Sep 2011 @ Noida / Hyderabad / Bangalore / Vizag

Jobs

(EXPERIENCED) Walk-In @ "INFOTECH" : ASIC & FPGA : On 24, 25 Sep 2011 @ Noida / Hyderabad / Bangalore / Vizag Sep 22nd 2011, 14:37 (Experienced) Walk-In : ASIC & FPGA @ Noida   Job Position : ASIC & FPGA Job Designation : Tech. Lead/Project Lead Job Category : Engineering Design, R&D Desired Experience : 2 to 10 Years (Mandatory)   Desired Skills : ASIC VERIFICATION (Job Code: ASIC-V) Job Location : Hyderabad / Bangalore Experience : 2 to 10 years' experience in the following areas: Multiple skills required : • Expertise in System Verilog & OVM. • Expertise in System Verilog & e-specman. • Expertise in Mixed Signal Verification. ASIC PHYSICAL DESIGN (Job Code: ASIC- PD) Job Location : Hyderabad / Bangalore / Vizag / Noida Experience : 2 to 10 years' experience in the following areas: • Partitioning, IO ring preparation, Floor Planning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop analysis, Physical verification, Signal Integrity, Low Power design. ASIC IMPLEMENTATION (Job Code: ASIC-IMP) Job Location : Hyderabad / Bangalore / Noida Experience : 2 to 10 years' experience in the following areas: • Logic Synthesis, Low Power Synthesis, Timing Constraints, Timing Closure, Static Timing Analysis, Cross talk analysis and Repair, Formal Verification. ASIC DFT (Job Code: ASIC-DFT) Job Location : Hyderabad / Bangalore / Vizag Experience : 2 to 10 years' experience in the following areas: • Basic logic design, Verilog RTL and verification back ground with exposure to STA utilizing industry standard tools. • Must possess a strong knowledge of DFT including JTAG, Boundary scan, MBIST, LBIST, scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan for at speed testing. Expertise in industry standard EDA tools for DFT such as DFTAdvisor, fastscan/TestKompress, TetraMax, LogicVision. Experience in Full-Chip DFT implementation of Scan, EDT/Adaptive Scan, JTAG, MBIST, Transition and Path delay ATPG. Experience in Gate Level Simulations, Synthesis, STA and Formal Verification. Understanding of ATE and test engineering. Post-Silicon debug. Programming in Perl, tcl, awk and c/c++. Experience in DFT with Logic Vision tools is mandatory. FPGA Engineers (Job Code: FPGA) Job Location : Hyderabad Experience : 2 to 10 years' experience in the following areas : • Ability to interface with silicon companies and understand their requirements and expectations. Rapidly adapt to different design and verification environments. Coordinate efforts with offshore design and verification teams. Strong experience using System Verilog & OVM / VMM. Experience in Test Benches • ACTEL based experience would be an added advantage Qualification for all the above positions : BE/B.Tech or ME/M.Tech/MS in respective streams Job Description : • We are conducting Scheduled Walk-in Drive for Hitech ASIC at Noida on 24th & 25th Sep 2011 (Sat. & Sun.) Please Carry (mandatory) : • Updated Resume Copy • Photo ID Proof • Latest Pay Slips • Academic Qualification Documents, Experience certificate • Passport Size Photograph Walk-In Date : On 24th, 25th September 2011 : 10 AM to 3 PM   Walk-In Venue : Infotech Enterprises Ltd, B-11, Sector 63, Noida 201301 Contact Person : Mr. Praveen Vemula   Contact Number : +91-40-23007455/23007462

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