Friday, August 5, 2011

Jobs: (FRESHERS) "HP | FIDELITY | SEED INFOTECH | TEAM GROUP | PERMEATIVE" : Off-Campus : BE / B.Tech / MCA : 2011 Passout : On 5-10 Aug 2011 @ Bangalore

Jobs
(FRESHERS) "HP | FIDELITY | SEED INFOTECH | TEAM GROUP | PERMEATIVE" : Off-Campus : BE / B.Tech / MCA : 2011 Passout : On 5-10 Aug 2011 @ Bangalore
Aug 5th 2011, 11:33

Campus Select India Pvt Ltd
http://www.ChetanaS.org
- Exclusive Job for Chetanaites...

Recruitment for our Clients - MNC COMPANIES

Dear ChetanaS,

We would like to publish below job requirement in your ChetanaSforum.com

Freshers : Off-Campus : BE / B.Tech / MCA : 2011 Passout Only @ Bangalore

Below requirements are for 2011 BE/B.Tech having 50% and above academic cut off.

..................................................

HP
http://www.ChetanaS.org
Job Position : Technical Support Engineer

Interview Location : Bangalore, Karnataka

Job Location : Bangalore, Karnataka

Eligibility Criteria :
• BE/B.Tech (CS, IS, IT, ECE, EEE and Telecom) 2011 pass outs
• Percentage cut off: 50% and above

Salary : Best in Industry

Joining : Immediate

Interview Date : 16th August 2011

..................................................

Fidelity
http://www.ChetanaS.org
Job Position : Process Associate (Non Voice Process)

Interview Location : Bangalore, Karnataka

Job Location : Bangalore, Karnataka

Eligibility Criteria :
• BE/B.Tech 2011 passouts
• Percentage cut off : Any percentage

Salary : Best in Industry (plus transport facility, night shift allowance, attendance incentives and pg accommodation)

Joining : Immediate

Interview Date : 17th August 2011

..................................................

Other opportunities available for candidates above 50% in the month of August

Company : Seed Infotech
Profile: IMS (Infrastructure Management Services)
Qualification : BE/BTech (CS, IS, IT, ECE, EEE and Telecom) 2011 passouts
Percentage cut off : 55% and above in academics
Salary: Best in Industry

Company : Team Group India
Profile: Trainee Engineers (Mysql and database management)
Qualification : BE/BTech (CS, IS, IT, ECE, EEE and Telecom) 2011 passouts
Percentage cut off : 55% and above in academics
Salary: Best in Industry

And many more...

..................................................

Campus Select provides opportunity for Tech Support Engineer, IMS (Infrastructure Management Services), Networking Profile, Software Trainee, Marketing profiles and Process Associate profile for BE/BTech candidates below 60% cut off in their academics.

Candidates above 60% throughout their academics will get opportunities for IT/Software/Testing profiles.

Upcoming drive for candidates above 60%.

Company : Permeative Technologies
Profile: Smart Phone Application Developers
Qualification : BE/BTech(CS,IS,IT, ECE) and MCA 2011 passouts
Percentage cut off : 65% and above throughout the academics
Job Location / Joining : Bangalore / Immediate
Interview: 13th August 2011

..................................................

How to Register ?

Become a Premium Member of Campus Select to get unlimited job opportunities till December 2011.

Benefits of Premium Member :
· Unlimited Job opportunities till December 2011
· Free The of Employability Assessment test (TEA Test) - powered by Merittrac
· Free Career guidance
· Free access to Online application to manage profile
· Get continuous SMS and Email updates on all job openings

This job opening is available for premium members of Campus Select (I) Pvt Ltd. You can become a premium member by visiting our office mentioned below.

Registration Date : From 5th to 10th August 2011 (Sunday Holiday)

Registration Timings :
Monday to Friday : 9.30 AM to 5.30 PM
Saturday : 9.30 AM to 12.30 PM
Sunday : Holiday

Registration Fees : Membership Fees applicable
http://www.ChetanaS.org
To register for the drives Visit :
Campus Select India Pvt Ltd,
# 168, 9th Cross, Off CMH Road,
Indiranagar Ist Stage,
Bangalore - 560038

http://www.ChetanaS.org
Contact Number : +91-80-42042561

Note :
• Already Premium Members need not register again, you will keep getting the opportunities by SMS and Email.
• Last date to apply for these companies 10th August 2011.

..................................................

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Jobs: (FRESHERS) "HCL" : Off-Campus : Openings for BE / B.Tech / MCA / ME / M.Tech / B.Sc @ All India

Jobs
(FRESHERS) "HCL" : Off-Campus : Openings for BE / B.Tech / MCA / ME / M.Tech / B.Sc @ All India
Aug 5th 2011, 10:54

Dear HCLite,

At HCL, it has always been our aim to recruit the crème-de-la-crème from across campuses in the country. And we believe that as an important member of this organization, you can help us achieve that aim. We are giving you an exclusive opportunity to introduce your friends to the many opportunities that are available at HCL and usher them to success.

We are currently looking for dynamic, young graduates with a desire to excel, and need your help in finding and bringing in the best! If you know graduates of the 2011 batch who satisfy the following criteria, please ask them to register at the following link:

http://hclcampusregistration.cloudapp.net/

Basic eligibility criteria:
1. A minimum of 65% aggregate in Class 10, 12 & Graduation are a must in the below mentioned disciplines
Ø BE, MCA, M.Tech, ME – CS / IT / ECE / EEE / E&I
Ø B.SC (Comp Sc / IT / Math / Physics / Electronics / Stats), BCA, B.Com (CS / IT)
2. All candidates should have graduated as part of the 2011 batch
3. Candidates should have no arrears at the time of registration
4. Candidates should have excellent verbal and written communication skills

Note:
1. This registration is open only for candidates who have graduated in 2011
2. Fresher referrals are not covered under the referral policy, please refer to Natasha for details
3. We are NOT hiring graduates from 2009 and 2010 under this category

Regards,
Team HR

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Jobs: Jobs in Ministry of Science and Technology Pakistan

Jobs
Jobs in Ministry of Science and Technology Pakistan
Aug 5th 2011, 17:55

Jobs in Ministry of Science and Technology Pakistan

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Jobs: Jobs in Industrial Estates Punjab Pakistan

Jobs
Jobs in Industrial Estates Punjab Pakistan
Aug 5th 2011, 17:44

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Jobs: Jobs Opportunity in Punjab Industries And Investment Department

Jobs
Jobs Opportunity in Punjab Industries And Investment Department
Aug 5th 2011, 17:36

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Jobs: Jobs in Walton Cantonment Board Cantt

Jobs
Jobs in Walton Cantonment Board Cantt
Aug 5th 2011, 18:03


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Jobs: (FRESHERS) Walk-In @ "KRDS SOFTWARE" : PHP Developers : On 20 Aug 2011 @ Chennai

Jobs
(FRESHERS) Walk-In @ "KRDS SOFTWARE" : PHP Developers : On 20 Aug 2011 @ Chennai
Aug 5th 2011, 12:07

KRDS Software Development Pvt. Ltd. (www.krds.in)
http://www.ChetanaS.org
- Exclusive Job for Chetanaites...

Incorporated in 2008, KRDS is a well established company that ideates and develops successful social media applications. KRDS is the No. 1 company in France for Facebook application development with operations in Spain, Italy, Belgium & Switzerland.

Dear ChetanaS,

We would like to publish below job requirement in your ChetanaSforum.com

(0-3 Years) Walk-In : PHP Developers @ Chennai
http://www.ChetanaS.org
Job Position : PHP Developer

Job Designation : Software Developer

Job Category : IT / Software

Walk-In Location : Chennai, Tamilnadu

Job Location : Chennai, Tamilnadu

Compensation : Rs 1,00,000 - 3,00,000 + Benefits

Number of Vacancies : 5

Desired Qualification : Any Graduate

Desired Experience : 0-3 Years

Mandatory Skills : PHP, MySQL
http://www.ChetanaS.org
Desired Skills :
• Candidates with Good Analytical & Communication Skills and academics.
• Candidates with good theoretical knowledge in Open Source Technology such as PHP, Mysql, Jquery, Ajax etc.
• Freshers can apply only if they have good theoretical knowledge in PHP.
http://www.ChetanaS.org
Keywords :
• PHP, MySql, Opensource, Javascript, Drupal
http://www.ChetanaS.org
Please Carry (mandatory) :
• Updated Resume Copy
• A printout of this ChetanaS job posting
• Photo ID proof

Note: Candidates without knowledge/experience in 'PHP, MySQL' - Please do NOT apply.

Note: You can mention the reference as 'ChetanaS'.

Walk-In Date : On 20th August 2011 (Saturday) : 10 AM to 3 PM
http://www.ChetanaS.org
Walk-In Venue :
KRDS Software Development,
Tidel Park, Taramani,
4th Floor, D Block South,
No 4, Rajiv Gandhi Salai,
Chennai - 600113

http://www.ChetanaS.org
Contact Person : Lokesh

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Jobs: Bank of India Specialist Officer Jobs

Jobs
Bank of India Specialist Officer Jobs
Aug 5th 2011, 17:06


Post published by BS for bankjob.blogspot.com

Bank of India (BOI)
(A Public Sector Undertaking)  sarkari-naukri.blogspot.com
Star House, Plot C-5, "G" Block, Bandra-Kurla Complex, Bandra (East), Mumbai  - 400051

Bank of India (BoI) invites applications for recruitment of  following Specialist Officers :
  1. Marketing Executive (MBA)  JMG-I scale  :  14 posts, Age : 21-30 years, Pay Scale : Rs.14500-25700
  2. Marketing Executive (MBA)  Scale-II :  278 posts, Age : 21-30 years, Pay Scale : Rs.19400-25100
  3. Law Officers JMG-I scale  :  03 posts, Age : 21-30 years, Pay Scale : Rs.14500-25700
Application Fee :  Rs.400/- (No fee for SC/ST/PWD/ExSM) to be deposited in the any branch of Bank of India through a Challan

How to Apply : Eligible candidates are advised to apply 'ONLINE' at the Bank of India Website only upto  16/08/2011

For more information, please view document  http://www.bankofindia.co.in/UserFiles/File/NoticeLawOfficers.doc  , Payment Challans are vailable at  http://www.bankofindia.co.in/UserFiles/File/ChallanFormat.doc and  link to apply online is available at http://registration.sifyitest.com/boisoaug11/

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Jobs: JNTU-KAKINADA : Revised Course Structure and Syllabus-B.Tech (CSE and IT)-II YEAR-I Semester (R10 Students).

Jobs
JNTU-KAKINADA : Revised Course Structure and Syllabus-B.Tech (CSE and IT)-II YEAR-I Semester (R10 Students).
Aug 5th 2011, 16:06

JNTU-KAKINADA : Revised Course Structure and Syllabus-B.Tech (CSE and IT)-II YEAR-I Semester (R10 Students).

JNTU-KAKINADA : Revised Course Structure and Syllabus-B.Tech (CSE and IT)-II YEAR-I Semester (R10 Students).

II B.TECH. – I SEMESTER (COMMON FOR COMPUTER SCIENCE ENGINEERING AND INFORMATION TECHNOLOGY)

REVISED COURSE STRUCTURE AND SYLLABUS – 2010-11 BATCH

II Year – I Semester

I SEMESTER P C

S.No.

Subject P C
1 Managerial Economics and Financial Analysis 4+1* 4
2 Probability & Statistics 4+1* 4
3 Mathematical Foundations of Computer  Science and Engineering 4+1* 4
4 Digital Logic Design 4+1* 4
5 Electronic Devices and Circuits 4+1* 4
6 Data Structures 4+1* 4
7 Electronic Devices and Circuits Lab 3 2
8 Data Structures Lab 3 2
9 Professional Communicational skills 2 1
Total Credits 29

*Tutorial



JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY KAKINADA

B.TECH. (COMPUTER SCIENCE AND ENGINEERING)

II Year B.Tech. – I Semester

DIGITAL LOGIC DESIGN

Unit  I : Number Systems

Binary, Octal, Decimal, Hexadecimal Number Systems. Conversion of Numbers From One Radix To Another Radix , r's Complement and (r-1)'s Complement Subtraction of Unsigned Numbers, Problems, Signed Binary Numbers, Weighted and Non weighted codes

Unit II:Logic Gates And Boolean Algebra

Basic Gates NOT, AND, OR, Boolean Theorms,Complement And Dual of Logical Expressions, Universal Gates, Ex-Or and Ex-Nor Gates, SOP,POS, Minimizations of Logic Functions Using Boolean Theorems, Two level Realization of Logic Functions Using Universal Gates.  Verilog programming for the minimized logic functions.

Unit III: Gate- Level Minimization

Karnaugh Map Method(K-Map): Minimization of Boolean Functions maximum upto  Four Variables , POS And SOP, Simplifications With Don't Care Conditions Using K-Map.

Unit IV: Combinational Arithmetic Logic Circuits

Design of Half Adder, Full Adder, Half Subtractor ,  Full Subtractor, Ripple Adders and Subtractors, Ripple Adder/Subtractor Using Ones and Twos Complement Method. Serial Adder , Carry Look Ahead Adder.

Unit V: Combinational Logic Circuits

Design of Decoders, Encoders, Multiplexers, Demultiplexers, Higher Order Demultiplexers and Multiplexers, Realization of Boolean Functions Using Decoders and Multiplexers, Priority Encoder, Code Converters, Magnitude Comparator.

Unit VI:  Introduction to Programmable Logic Devices (PLOs)

PLA, PAL, PROM. Realization of Switching Functions Using PROM, PAL and PLA. Comparison of PLA, PAL and PROM..

Unit VII: Introduction to Sequential Logic Circuits

Classification of Sequential Circuits, Basic Sequential Logic Circuits: Latch and Flip-Flop, RS- Latch Using NAND and NOR Gates, Truth Tables. RS,JK,T and D Flip Flops , Truth and Excitation Tables, Conversion of Flip Flops. Flip Flops With Asynchronous Inputs (Preset and Clear).

Unit VIII: Registers and Counters

Design of Registers, Buffer Register, Control Buffer Registers, Bidirectional Shift Registers, Universal Shift Register, Design of Ripple Counters, Synchronous Counters and Variable Modulus Counters, Ring Counter, Johnson Counter.

TEXT BOOKS :

1. Digital Design ,4/e, M.Morris Mano, Michael D  Ciletti, PEA

2. Fundamentals of Logic Design, 5/e, Roth, Cengage

REFERENCE  BOOKS :

1. Switching and Finite Automata Theory,3/e,Kohavi, Jha, Cambridge.

2. Digital Logic Design, Leach, Malvino, Saha,TMH

3.Modern Digital Electronics, R.P. Jain, TMH



B.TECH. (COMPUTER SCIENCE AND ENGINEERING)

II Year B.Tech. – I Semester

ELECTRONIC DEVICES AND CIRCUITS

Unit-I

Electron Ballistics and Applications: Force on Charged Particles in Electric field, Constant Electric Field, Potential, Relationship between Field Intensity and Potential, Two Dimensional Motion, Electrostatic Deflection in Cathode ray Tube, CRO, Force in Magnetic Field, Motion in Magnetic Field, Magnetic Deflection in CRT, Magnetic Focusing, Parallel Electric and Magnetic fields and Perpendicular Electric and Magnetic Fields.

Unit- II

Review of Semi Conductor Physics : Insulators, Semi conductors, and Metals classification using Energy Band Diagrams, Mobility and Conductivity, Electrons and holes in Intrinsic Semi conductors, Extrinsic Semi Conductor, (P and N Type semiconductor) Hall effect, Generation and Recombination of Charges, Diffusion, Continuity Equation, Injected Minority Carriers, Law of Junction, Fermi Dirac Function, Fermi level in Intrinsic and Extrinsic Semiconductor

Unit- III

Junction Diode Characteristics  : Open circuited P N Junction, Forward and Reverse Bias, Current components in PN Diode, Diode Equation,Volt-Amper Characteristic, Temperature Dependence on V – I characteristic, Step Graded Junction, Diffusion Capacitance and Diode Resistance (Static and Dynamic), Energy Band Diagram of PN Diode,

Special Diodes: Avalanche and Zener Break Down, Zener Characterisitics,  Tunnel Diode, Characteristics with the help of Energy Band Diagrams, Varactor Diode, LED, PIN Diode,  Photo Diode

Unit IV

Rectifiers and Filters: Half wave rectifier, ripple factor, full wave rectifier(with and without transformer), Harmonic components in a rectifier circuit, Inductor filter, Capacitor filter, L- section filter, P- section filter, Multiple L- section and Multiple  P section filter, and comparison of various filter circuits  in  terms of ripple factors, Simple circuit of a regulator using zener diode, Series and Shunt voltage regulators

Unit- V

Transistors :

Junction transistor, Transistor current components, Transistor as an amplifier, Characteristics of Transistor in Common Base and  Common Emitter Configurations, Analytical expressions for Transistor Characteristics, Punch Through/  Reach Through, Photo Transistor, Typical transistor junction voltage values.

Unit VI

Field Effect Transistors:

JFET characteristics (Qualitative and Quantitative discussion), Small signal model of JFET, MOSFET characteristics (Enhancement and depletion mode), Symbols of MOSFET, Introduction to SCR and UJT and their characteristics,

UNIT-VII

Transistor Biasing and Thermal Stabilization : Transistor Biasing and Thermal Stabilization: Operating point, Basic Stability, Collector to Base Bias, Self Bias Amplifiers, Stabilization against variations in VBE,, and ? for the self bias circuit, Stabilization factors, (S, S', S''), Bias Compensation,  Thermistor and Sensitor compensation,   Compensation against variation in VBE, Ico,,  Thermal runaway, Thermal stability

UNIT- VIII

Small signal low frequency Transistor models: Two port devices and the Hybrid model, Transistor Hybrid model, Determination of h-parameters from characteristics, Measurement of h-parameters, Conversion formulas for the parameters of three transistor configurations, Analysis of a Transistor Amplifier circuit using h- parameters, Comparison of Transistor Amplifier configurations

Text Books

1.  Electronic Devices and Circuits – J. Millman,  C.C. Halkias,  Tata Mc-Graw Hill

Reference

1.  Electronic Devices and Circuits – K Satya Prasad,  VGS Book Links

2.  Integrated Electronics – Jacob Millman,  Chritos C. Halkies,, Tata Mc-Graw Hill, 2009

3. Electronic Devices and Circuits – Salivahanan, Kumar, Vallavaraj, TATA McGraw Hill, Second Edition

4. Electronic Devices and Circuits – R.L. Boylestad and Louis Nashelsky, Pearson/Prentice Hall,9thEdition,2006

5. Electronic Devices and Circuits -BV Rao, KBR Murty, K Raja Rajeswari, PCR Pantulu, Pearson, 2nd edition

***


B.TECH. (COMPUTER SCIENCE AND ENGINEERING)

II Year B.Tech. – I Semester

DATA STRUCTURES

UNIT I: Recursion and Linear Search:

Preliminaries of algorithm,  Algorithm analysis and complexity.

Recursion: Definition, Design Methodology and Implementation of recursive algorithms, Linear and binary recursion, recursive algorithms for factorial function, GCD computation, Fibonacci sequence, Towers of Hanoi, Tail recursion

List Searches using Linear Search, Binary Search, Fibonacci Search,

UNIT II: Sorting Techniques:

Basic concepts, Sorting by : insertion (Insertion sort), selection (heap sort), exchange (bubble sort, quick sort), distribution (radix sort ) and merging  (merge sort )  Algorithms.

UNIT III: Stacks and Queues:

Basic Stack Operations, Representation of a Stack using Arrays, Stack Applications: Reversing list,   Factorial Calculation, In-fix- to postfix Transformation, Evaluating Arithmetic Expressions.

Queues: Basic Queues Operations, Representation  of a  Queue using array, Implementation of Queue Operations using Stack,  Applications of Queues-Round robin Algorithm, Enqueue,  Dequeue, Circular Queues,   Priority Queues.

UNIT IV:  Linked Lists:

Introduction, single linked list, representation of a linked list in memory, Operations on a single linked list, merging two single linked lists into one list, Reversing a   single  linked list, applications of single linked list to represent polynomial expressions and sparse matrix manipulation, Advantages and disadvantages of single  linked list, Circular linked list,  Double linked list

UNIT V: Trees:

Basic tree concepts, Binary Trees: Properties, Representation of Binary Trees using arrays and linked lists, operations on a Binary tree , Binary Tree Traversals (recursive), Creation of binary tree from in-order and pre(post)order traversals,

UNIT VI: Advanced concepts of Trees:

Tree Travels using stack (non recursive), Threaded Binary Trees. Binary search tree, Basic concepts, BST operations: insertion, deletion,

Balanced binary trees – need, basics and applications in computer science (No operations )

UNIT VII: Graphs:

Basic concepts, Representations of Graphs: using Linked list and adjacency matrix, Graph algorithms

Graph Traversals (BFS & DFS), applications: Dijkstra's shortest path, Transitive closure, Minimum Spanning Tree using     Prim's Algorithm, warshall's Algorithm.

Unit VIII: Sets:

Definition, Representation of Sets using Linked list, operations of sets using linked lists, application of sets- Information storage using bit strings

Abstract Data Type Introduction to abstraction, Model for an Abstract Data Type, ADT Operations, ADT Data Structure, ADT Implementation of stack and queue .

TEXT BOOKS:

1.      Data Structures, 2/e, Richard F, Gilberg , Forouzan, Cengage

2.      Data Structures and Algorithms, 2008,G.A.V.Pai, TMH

REFERENCE  BOOKS:

1.      Data Structure with C, Seymour Lipschutz, TMH

2.      Classic Data Structures, 2/e, Debasis ,Samanta,PHI,2009

3.      Fundamentals of Data Structure in C, 2/e, Horowitz,Sahni, Anderson Freed,University Prees

B.TECH. (COMPUTER SCIENCE AND ENGINEERING)

II Year B.Tech. – I Semester

ELECTRONIC DEVICES AND CIRCUITS LAB

PART A : (Only for viva voce Examination)

ELECTRONIC WORKSHOP PRACTICE ( in 6 lab sessions) :

1. Identification, Specifications, Testing of R, L, C Components (Colour Codes), Potentiometers, Switches (SPDT, DPDT, and DIP), Coils, Gang Condensers, Relays, Bread Boards.

2. Identification, Specifications and Testing of Active Devices, Diodes, BJTs, Lowpower JFETs, MOSFETs, Power Transistors, LEDs, LCDs, Optoelectronic Devices, SCR, UJT, DIACs, TRIACs, Linear and Digital ICs.

3. Soldering practice – Simple Circuits using active and passive components.

4. Single layer and Multi layer PCBs (Identification and Utility).

5. Study and operation of

• Multimeters (Analog and Digital)

• Function Generator

• Regulated Power Supplies

  1. Study and Operation of CRO.

PART B : (For Laboratory examination – Minimum of 10 experiments)

1.  Frequency measurment using Lissajous Figures

2. PN Junction diode characteristics   A. Forward bias  B. Reverse bias.( cut-in voltage & Resistance calculations)

3. Zener diode characteristics and Zener as a regulator

4. Transistor CB characteristics (Input and Output) & h Parameter calculations

5. Transistor CE characteristics (Input and Output) & h Parameter calculations

6. Rectifier without filters (Full wave & Half wave)

7. Rectifier with filters (Full wave & Half wave)

8. FET characteristics

9. SCR Charecteristics

10. UJT Charectristics

11. CE Amplifier

12. CC Amplifier (Emitter Follower).

PART C:

Equipment required for Laboratories:

  1. Regulated Power supplies (RPS)                        -           0-30v
  2. CROs                                                              -           0-20M Hz.
  3. Function Generators                                         -           0-1 M Hz.
  4. Multimeters
  5. Decade Resitance Boxes/Rheostats
  6. Decade Capacitance Boxes
  7. Micro Ammeters (Analog or Digital)                 -           0-20 µA, 0-50µA, 0-100µA, 0-                                                                                              200µA
  8. Voltmeters (Analog or Digital)                         -           0-50V, 0-100V, 0-250V
  9. Electronic Components                                   -          Resistors, Capacitors, BJTs, LCDs,                                                                                        SCRs,  UJTs, FETs, LEDs,

MOSFETs,diodes,transistors

***

Click on the below link to Download the Official Notification :

JNTU-KKD : Revised Course Structure and Syllabus-B.Tech (CSE and IT)-II YEAR-I Semester (R10 Students).

||| FirstRanker.com ||| - JNTU Hyderabad - JNTU Kakinada - JNTU Anantapur - *A hub for all the JNTU students* *For all the latest updates related to JNTU*

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Jobs: JNTU-ANANTAPUR : B.Tech (CCC) III Year Syllabus of EEE,CIVIL,ECE & MECH.

Jobs
JNTU-ANANTAPUR : B.Tech (CCC) III Year Syllabus of EEE,CIVIL,ECE & MECH.
Aug 5th 2011, 16:23
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Jobs: Cognizant Recruitment drive on 6th August 2011

Jobs
Cognizant Recruitment drive on 6th August 2011
Aug 5th 2011, 15:27

This job is posted by TUSHAR and available at itjobsdelhi[dot]blogspot[dot]com Cognizant Technology Solutions India Ltd:Walk-In Drive on 6th August 2011 at Gurgaon, Bangalore, Chennai, Hyderabad and Pune For details please visit: http://www.naukri.com/customised/cognizant/cognizant-jointheleader/new.html This information is available at http://itjobsdelhi.blogspot.com. For Latest IT jobs in India please visit http://itjobsdelhi.blogspot.com

This Feed is available at http://itjobsdelhi[dot]blogspot[dot]com. For complete details of this job and for more IT & Engg. Jobs in India please visit http://itjobsdelhi[dot]blogspot[dot]com Subscribe at http://itjobsdelhi[dot]blogspot[dot]com


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Jobs: Jobs in Visveshvaraya Grameena Bank Aug-2011

Jobs
Jobs in Visveshvaraya Grameena Bank Aug-2011
Aug 5th 2011, 01:35


Published by Manisha for sarkari-naukri.blogspot.com
Visveshvaraya Grameena Bank (VGB)
(Sponsored by Vijaya Bank)
Head Office: Post Box No 41, Vidyanagar, Mandya – 571401, Karnataka
sarkari-naukri.blogspot.com

Online applications are invited from Indian citizens, for the following  posts :
  • Officer Junior Manager Scale-I : 07 posts, Pay Scale : Rs.14500–25700/-
  • Office Assistants (Multipurpose) : 15 posts, Pay Scale : Rs.7200–19300/-
Application Fee  : Rs.350/-  (Rs.50/- for SC/ST/PWD/EXS) to be deposited in any branch of Vijaya Bank.

How to Apply : Candidates are required to apply Online only  through Visveshvaraya Grameena Bank, website up to 30/08/2011.

Please visit http://www.vgbank.in/VG%20Bank/recrutment.htm  for details and Challan   and Online application form.

Published by Manisha for sarkari-naukri.blogspot.com
(Click on the Labels below for more similar Jobs)

Compiled by Manisha for her blog http://sarkari-naukri.blogspot.com/ for providing Government Jobs available in India. .  Other Blogs are

http://www.hindi-blog.com and Friendly blog is http://bankjob.blogspot.com

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Jobs: ENGAGEMENT OF AYUSH (AYURVEDIC PHYSICIAN-01), BADDI, HP

Jobs
ENGAGEMENT OF AYUSH (AYURVEDIC PHYSICIAN-01), BADDI, HP
Aug 5th 2011, 01:28


Walk-in-interview for the post of Ayurvedic Physician, on one year contract basis extendable up to 3 years or till the posts is filled up on regular basis whichever is earlier at ESIC Model Hospital, Village: Katha, Baddi, H.P.. Accordingly, the eligible and desirous candidates fulfilling the qualifications/eligibility conditions as under should appear for a walk-in-interview with their application along with original certificates and one set of attested photocopy of the relevant documents in support of Age, Qualifications, Attempt, Mark Sheet, MCI/State Registration, Category & experience certificate etc. and two recent passport size photographs:-
AYUSH (AYURVEDIC, HOMEOPATHY & YOGA INSTRUCTOR)
No. of posts:-
Ayurvedic-01,
Qualifications:-
Ayurvedic-BAMS.
Emoluments per month:-
Ayurvedic-8000/-
Age on 10/08/2011 not exceeding 35 years for Ayurvedic
Date of interview:- 22/08/2011

Note:-
1. All the candidates should report in the office of Medical Superintendent, Village: Katha, Opposite Gillette Factory, Baddi, H.P. at 10:00 A.M. to 4:00 P.M. on the stipulated date(s). Candidates reporting after 4:00 P.M. will not be considered for walking interview.
2. The Number of vacancies may likely be change.
3. No TA/DA will be paid to the candidates for appearing in the interview.
4. This advertisement has also been uploaded on website www.esic.nic.in
5. The competent authority reserves the right to fill up of all or not to fill up any post.
MEDICAL SUPERINTENDENT

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Jobs: Advertisement for the Post of Professor, Reader & Lecturer, Kanchanwadi

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Advertisement for the Post of Professor, Reader & Lecturer, Kanchanwadi
Aug 5th 2011, 01:46

Advertisement No.38/2011 
C.S.M.S.S.'s Ayurved Mahavidyalaya, Paithan Road, Kanchanwadi, Dist. Aurangabad - 431 002
Last Date: 20/08/2011


For more details CLICK HERE.

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